Modern integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding. Wafer level chip scale packaging (WLCSP) is currently widely used for its low cost and relatively simple processes. In a typical WLCSP, interconnect structures are formed on metallization layers, followed by the formation of under-bump metallurgy (UBM), and the mounting of solder balls.
Flip-chip packaging utilizes bumps to establish electrical contact between a chip's I/O pads and the substrate or lead frame of the package. Structurally, a bump actually contains the bump itself and a so-called under bump metallurgy (UBM) located between the bump and an I/O pad. An UBM generally contains an adhesion layer, a barrier layer and a wetting layer, arranged in this order on the I/O pad. The bumps themselves, based on the material used, are classified as solder bumps, gold bumps, copper pillar bumps and bumps with mixed metals. Recently, copper interconnect post technology is proposed. Instead of using solder bump, the electronic component is connected to a substrate by means of copper post. The copper interconnect post technology achieves finer pitch with minimum probability of bump bridging, reduces the capacitance load for the circuits and allows the electronic component to perform at higher frequencies. A solder alloy is still necessary for capping the bump structure and jointing electronic components as well.
Usually, a material used for the solder alloy is so-called Sn—Pb eutectic solder of Sn-38 mass % Pb. In recent years, it is urged to put Pb-free solder to practical use. The binary Sn—Ag alloy is used as the lead-free solder with Ag between 2.0˜4.5 weight percent, which melts at a temperature between 240˜260° C. The reflow soldering process and equipment for lead-free components are similar to conventional eutectic solder. Many developments of solder alloys have been directed to make the composition of an alloy, as close as possible to the eutectic composition of that in order to use the eutectic point to avoid thermal damage. However, the melting point of a Pb-free solder material is higher than that of the conventional Sn—Pb eutectic solder, so that there arises problems of cracks and stress reliability issues as TCB testing, especially to large die size. Even applied to the Cu post technology, the flip-chip assembly using the Pb-free solder material as the cap still suffers the crack issue induced by die edge/substrate interface stress.